Senior Product Manager, Hardware (NPU IP)

Own the Chimera GPNPU IP roadmap as Senior Product Manager, Hardware (NPU IP), covering feature definition, architecture freezes, and anchor SoC customer integration for production devices shipping in 2027 and beyond.

Responsibilities

• Translate customer requirements, competitive pressures, and architectural constraints into track-by-track feature lists with explicit gating.
• Build the business and technical case for contested architecture decisions.
• Lead trade-off reviews with architects and deliver clear recommendations to the Product Steering Committee (PSC).
• Drive IP usability by identifying silent customer workarounds (API wrappers, custom RTL hooks, glue logic) and productizing proper architectural solutions when required.
• Act as the named hardware product owner for key anchor accounts, presenting new features and integrating formal architecture feedback into the product roadmap.
• Conduct architecture reviews with technical buyers, including Tier-1 automotive and OEM SoC design teams.
• Partner with international customers, with a focus on supporting key anchor accounts in the Japanese and global semiconductor markets.
• Analyze competitive architectures (Synopsys NPX6, Arm Ethos-U85, Ceva NeuPro-M, NVIDIA Jetson) to anticipate market needs and inform product requirements before gaps appear in customer evaluations.
• Define and position SoC integration features, specifying which knobs are exposed and productized, including AXI4/ACE-Lite, CoreSight, power domains, and performance counters.
• Sequence functional safety positioning, including lockstep configurations, FMEDA work, and safety-island architectures for automotive and critical application standards.

Requirements

• 5–8 years of Product Management experience focused on hardware or silicon products, with a senior IC background.
• Direct experience in at least two of the following: NPU/AI accelerator architecture, SoC integration, DSP/vector compute, automotive silicon, or semiconductor IP licensing.
• Proven ability to lead technical architecture reviews with sophisticated buyers (Tier-1 automotive, OEM SoC teams).
• Active adoption of agentic AI tools (e.g., Claude Code, Cursor, or equivalent) in daily workflows.
• EE/CE/CS engineering degree (or equivalent depth).
• Based in or willing to relocate to the Bay Area (Burlingame hybrid model).
• Willing to travel quarterly (domestic and international).

Technologies

• Claude Code
• Cursor
• AXI4
• ACE-Lite
• CoreSight

What Success Looks Like

• Freeze and lock in next-generation GPNPU IP feature sets (QC/QD releases) aligned with target customer tape-out schedules.
• Lead technical architecture reviews with anchor Tier-1/OEM accounts and convert feedback into actionable roadmap tracks.
• Productize key integration and usability knobs to streamline customer IP integration cycles.

Preferred

• Prior RTL or silicon-implementation background (e.g., shipped a block, went through tape-out, or owned a microarchitecture spec).
• Experience working at a semiconductor IP vendor (e.g., Synopsys, Arm, Ceva, Cadence, Imagination, VeriSilicon).
• Direct exposure to AI/ML compute stack architectures (dataflow, quantization, sparsity, mixed-precision trade-offs).
• Experience engaging with Japanese-market customers and technical teams.

Benefits

• Medical, dental, and vision insurance from day one, with premiums covered at 99% for Employees.
• Company-paid life insurance.
• Voluntary supplemental life insurance.
• STD + LTD insurance.
• Commuter support including parking or Caltrain reimbursement.
• FSA + HSA.
• Equity with the business.
• Paid Parental Leave.
• 401(k) Retirement Plan.
• Flexible PTO.
• Winter holiday shutdown.
• Catered lunch each day in the office.
• Downtown Burlingame office location near shops, cafes, and local amenities.

Compensation

• Base salary: $200,000 to $250,000 per year.
• Eligible for equity and a discretionary annual performance bonus as applicable to role and level.